Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 145
PIC18F87J10 FAMILY
TABLE 11-17: PORTH FUNCTIONS
TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16
RH0
0
O
DIG
LATH<0> data output.
1
I
ST
PORTH<0> data input.
A16
x
O
DIG
External memory interface, address line 16. Takes priority over port data.
RH1/A17
RH1
0
O
DIG
LATH<1> data output.
1
I
ST
PORTH<1> data input.
A17
x
O
DIG
External memory interface, address line 17. Takes priority over port data.
RH2/A18
RH2
0
O
DIG
LATH<2> data output.
1
I
ST
PORTH<2> data input.
A18
x
O
DIG
External memory interface, address line 18. Takes priority over port data.
RH3/A19
RH3
0
O
DIG
LATH<3> data output.
1
I
ST
PORTH<3> data input.
A19
x
O
DIG
External memory interface, address line 19. Takes priority over port data.
RH4/AN12/P3C
RH4
0
O
DIG
LATH<4> data output.
1
I
ST
PORTH<4> data input.
AN12
I
ANA
A/D input channel 12. Default input configuration on POR; does not affect
digital output.
digital output.
P3C
(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH5/AN13/P3B
RH5
0
O
DIG
LATH<5> data output.
1
I
ST
PORTH<5> data input.
AN13
I
ANA
A/D input channel 13. Default input configuration on POR; does not affect
digital output.
digital output.
P3B
(1)
0
O
DIG
ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH6/AN14/P1C
RH6
0
O
DIG
LATH<6> data output.
1
I
ST
PORTH<6> data input.
AN14
I
ANA
A/D input channel 14. Default input configuration on POR; does not affect
digital output.
digital output.
P1C
(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH7/AN15/P1B
RH7
0
O
DIG
LATH<7> data output.
1
I
ST
PORTH<7> data input.
AN15
I
ANA
A/D input channel 15. Default input configuration on POR; does not affect
digital output.
digital output.
P1B
(1)
0
O
DIG
ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1:
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
are PORTE<6:3>.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
LATH
LATH7
LATH6
LATH5
LATH4
LATH3
LATH2
LATH1
LATH0
TRISH
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0