Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
PIC18F87J10 FAMILY
DS39663F-page 372
© 2009 Microchip Technology Inc.
FIGURE 27-12:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES)
TABLE 27-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES)
TABLE 27-15: PARALLEL SLAVE PORT REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
50
T
CC
L
CCPx Input Low
Time
Time
No prescaler
0.5 T
CY
+ 20
—
ns
With prescaler
10
—
ns
51
T
CC
H
CCPx Input
High Time
High Time
No prescaler
0.5 T
CY
+ 20
—
ns
With prescaler
10
—
ns
52
T
CC
P
CCPx Input Period
3 T
CY
+ 40
N
—
ns
N = prescale
value (1, 4 or 16)
value (1, 4 or 16)
53
T
CC
R
CCPx Output Fall Time
—
25
ns
54
T
CC
F
CCPx Output Fall Time
—
25
ns
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
62
TdtV2wrH
Data In Valid before WR
↑ or CS ↑ (setup time)
20
—
ns
63
TwrH2dtI
WR
↑ or CS ↑ to Data–In Invalid (hold time)
20
—
ns
64
TrdL2dtV
RD
↓ and CS ↓ to Data–Out Valid
—
80
ns
65
TrdH2dtI
RD
↑ or CS ↓ to Data–Out Invalid
10
30
ns
66
TibfINH
Inhibit of the IBF Flag bit being Cleared from
WR
WR
↑ or CS ↑
—
3 T
CY
Note:
Refer to Figure 27-3 for load conditions.
CCPx
(Capture Mode)
50
51
52
CCPx
53
54
(Compare or PWM Mode)