Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP PIC18F65J15-I/PT Data Sheet
Product codes
PIC18F65J15-I/PT
© 2009 Microchip Technology Inc.
DS39663F-page 373
PIC18F87J10 FAMILY
FIGURE 27-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
70
T
SS
L2
SC
H,
T
SS
L2
SC
L
SSx
↓ to SCKx ↓ or SCKx ↑ Input
T
CY
—
ns
73
T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDIx Data Input to SCKx Edge
20
—
ns
73A
T
B
2
B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
of Byte 2
1.5 T
CY
+ 40
—
ns
(Note 1)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDIx Data Input to SCKx Edge
40
—
ns
75
T
DO
R
SDOx Data Output Rise Time
—
25
ns
76
T
DO
F
SDOx Data Output Fall Time
—
25
ns
78
T
SC
R
SCKx Output Rise Time (Master mode)
—
25
ns
79
T
SC
F
SCKx Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDOx Data Output Valid after SCKx Edge
—
50
ns
Note 1: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
70
71
72
73
74
75, 76
78
79
80
79
78
MSb
LSb
bit 6 - - - - - - 1
MSb In
LSb In
bit 6 - - - - 1
Note:
Refer to Figure 27-3 for load conditions.