Microchip Technology DV164136 Data Sheet

DS80343B-page 2

© 2009 Microchip Technology Inc.

If the module is in I

2

C Master mode and the slave

performs clock stretching, the first clock pulse after
the slave releases the SCL line may be narrower
than the configured clock width. This may result in
the slave missing the first clock in the next
transmission/reception.

If the module is in I

2

C Master mode, do not have

the slave perform clock stretching. Alternately, the
master can slow down the SCL clock frequency to
a level where the slave can detect the narrowed
clock pulse.

All engineering and production devices.

In rare situations when interrupts are enabled,
unexpected results may occur if:

• The EUSART is disabled (the SPEN 

(RCSTAx <7>) bit = 0)

• The EUSART is re-enabled (RCSTAx <7> = 1)

• A two-cycle instruction is executed

Add a 2-T

CY

 delay after re-enabling the EUSART.

1.

Disable the receive interrupts:

• For RCSTA1 – RC1IE bit (PIE1<5>) = 0

• For RCSTA2 – RC2IE bit (PIE3<5>) = 0

2.

Disable the EUSART:

• For RCSTA1 – SPEN bit (RCSTA1<7>) = 0

• For RCSTA2 – SPEN bit (RCSTA2<7>) = 0

3.

Re-enable the EUSART (RCSTAx <7> = 1).
(See step 1.)

4.

Re-enable the receive interrupts:

• For RCSTA1 – RC1IE bit (PIE1<5>) = 1

• For RCSTA2 – RC2IE bit (PIE3<5>) = 1

(This is the first T

CY

 delay.)

5.

Execute a NOP instruction.
(This is the second T

CY

 delay.)

All engineering and production devices.

When Timer1 is running on the Timer1 oscillator, if
Sleep mode is executed immediately after loading
Timer 1 with 0xFFFF, the Timer1 interrupt will not
get set on the first overflow from 0xFFFF to
0x0000.

All subsequent overflows, from 0xFFFF to 0x0000,
will work correctly.

None.

All engineering and production devices.