Microchip Technology MA330019-2 Data Sheet

© 2007-2012 Microchip Technology Inc.

DS70292G-page 107

  

U-0

R/W-0

R/W-0

U-0

U-0

U-0

U-0

U-0

—

DMA4IE

PMPIE

—

—

—

—

—

bit 15

bit 8

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

—

DMA3IE

C1IE

C1RXIE

SPI2IE

SPI2EIE

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14

DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 13

PMPIE: Parallel Master Port Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 12-5

Unimplemented: Read as ‘0’

bit 4

DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request has enabled

bit 3

C1IE: ECAN1 Event Interrupt Enable bit

1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 2

C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit

1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 1

SPI2IE: SPI2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 0

SPI2EIE: SPI2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

Note 1: Interrupts are disabled on devices without ECAN™ modules.