Microchip Technology MA330019-2 Data Sheet

DS70292G-page 109

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

REGISTER 7-14:

IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

R/W-0

U-0

DAC1LIE

(2)

DAC1RIE

(2)

—

bit 15

bit 8

U-0

R/W-0

U-0

—

C1TXIE

(1)

DMA7IE

DMA6IE

CRCIE

U2EIE

U1EIE

—

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

DAC1LIE: DAC Left Channel Interrupt Enable bit

(2)

1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 14

DAC1RIE: DAC Right Channel Interrupt Enable bit

(2)

1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 13-7

Unimplemented: Read as ‘0’

bit 6

C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit

(1)

1 = Interrupt request occurred
0 = Interrupt request not occurred

bit 5

DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 4

DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 3

CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 2

U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 1

U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled

bit 0

Unimplemented: Read as ‘0’

Note 1: Interrupts are disabled on devices without ECAN™ modules.

2: Interrupts are disabled on devices without Audio DAC modules.