Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533H-page 20
2011-2014 Microchip Technology Inc.
EXAMPLE 4:
WORK AROUND CODE
Affected Families and Silicon Revisions
36. Module: PWM
When the PWM generator is configured to
operate in Current Reset mode (XPRES
(PWMCONx<1>) = 1 with Independent Time Base
mode (ITB (PWMCONx<9>) = 1), the PWM Reset
will happen only in every alternate PWM cycle.
operate in Current Reset mode (XPRES
(PWMCONx<1>) = 1 with Independent Time Base
mode (ITB (PWMCONx<9>) = 1), the PWM Reset
will happen only in every alternate PWM cycle.
Work around
1.
Generate an interrupt when the comparator
state changes. This interrupt should be high
priority and could be either a comparator
interrupt or PWM Fault interrupt. The
current-limit interrupt does not function in
this mode. Inside the interrupt, update
PHASEx (period value) with a value less
than the programmed duty cycle and then
immediately update the PHASEx register
with the value, as required by the application
(PWM_period), shown in
state changes. This interrupt should be high
priority and could be either a comparator
interrupt or PWM Fault interrupt. The
current-limit interrupt does not function in
this mode. Inside the interrupt, update
PHASEx (period value) with a value less
than the programmed duty cycle and then
immediately update the PHASEx register
with the value, as required by the application
(PWM_period), shown in
EXAMPLE 5:
WORK AROUND CODE
2.
When the External Current Reset signal is
applied to the PWM generator (configured
using Current-Limit Signal Source Select
bits (CLSRC<4:0>) in the PWM Fault
Current-Limit Control registers
(FCLCONx<14:10>), depending on the
PWM resolution selected, PCLKDIV<2:0>
(PTCON2<2:0>), the maximum pulse width
of the External Current Reset signal is to be
restricted to less than the values, as shown in
applied to the PWM generator (configured
using Current-Limit Signal Source Select
bits (CLSRC<4:0>) in the PWM Fault
Current-Limit Control registers
(FCLCONx<14:10>), depending on the
PWM resolution selected, PCLKDIV<2:0>
(PTCON2<2:0>), the maximum pulse width
of the External Current Reset signal is to be
restricted to less than the values, as shown in
Affected Families and Silicon Revisions
37. Module: Op Amp/Comparator
Op amp/comparator voltage reference can choose
its source either from V
its source either from V
REF
+ or AV
DD
, depending
on the CVRSS bit (CVRCON<4>) setting.
If the CVRSS bit is set to ‘1’, the comparator voltage
reference source will be CV
reference source will be CV
RSRC
= (V
REF
+) – (AV
SS
).
Due to this issue, if the CVRSS bit is set to ‘1’ and
the voltage on V
the voltage on V
REF
+ is less than 1.33V, the
op amp/comparator voltage reference will
malfunction.
malfunction.
Work around
None.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
—
dsPIC33/PIC24EP64 devices
A8
dsPIC33/PIC24EP128 devices
A8
dsPIC33/PIC24EP256 devices
—
dsPIC33/PIC24EP512 devices
A7
#define DESIRED_DEADTIME 100
if (PDCtemp < (DESIRED_DEADTIME/2))
{
ALTDTRx = PDCtemp * 2;
PDCx = PDCtemp;
}
else
{
ALTDTRx = DESIRED_DEADTIME;
PDCx = PDCtemp;
}
PWMx ISR:
{
PHASEx = PDCx - 100;
PHASEx = PWM_period;
PWMxIF =0;
}
TABLE 5:
MAXIMUM EXTERNAL CURRENT
RESET SIGNAL WIDTH
RESET SIGNAL WIDTH
PCLKDIV<2:0>
Max. External Current Reset
Signal Width (in nS)
000
20
001
40
010
80
011
160
100
320
101
640
110
1280
111
2560
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7