Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533H-page 8
2011-2014 Microchip Technology Inc.
5.
Module: UART
When using UTXISEL<1:0> = 01 (interrupt when
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register (TSR), the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register (TSR), the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Families and Silicon Revisions
6.
Module: Power System
The VREGSF bit functions as documented, but will
always read back as ‘0’. Because of the
Read-Modify-Write process, any BSET or BCLR
instruction of the RCON register will also write a ‘0’
to the VREGSF bit.
always read back as ‘0’. Because of the
Read-Modify-Write process, any BSET or BCLR
instruction of the RCON register will also write a ‘0’
to the VREGSF bit.
Work around
If the VREGSF bit is intended to be set to ‘1’, the
user software must also write a ‘1’ to the VREGSF
bit when setting or clearing any other bit in the
RCON register.
user software must also write a ‘1’ to the VREGSF
bit when setting or clearing any other bit in the
RCON register.
Affected Families and Silicon Revisions
7.
Module: ADC
The ADC Conversion Status (DONE) bit
(ADxCON1<0>) does not indicate completion of
conversion when an external interrupt is selected
as the ADC trigger source (SSRC<2:0> bits
(AD1CON1<7:5>) = 0x1).
(ADxCON1<0>) does not indicate completion of
conversion when an external interrupt is selected
as the ADC trigger source (SSRC<2:0> bits
(AD1CON1<7:5>) = 0x1).
Work around
Use an ADC interrupt or poll the ADxIF bit in the
IFSx registers to determine the completion of
conversion.
IFSx registers to determine the completion of
conversion.
Affected Families and Silicon Revisions
8.
Module: PTG
When using the strobe output step commands
(PTGCTRL 0x1110, PTGCTRL 0x1100 and
PTGCTRL 0x110
(PTGCTRL 0x1110, PTGCTRL 0x1100 and
PTGCTRL 0x110
) to write to the AD1CHS0
register, the PTGPWD<3:0> bits (PTGCON<7:4>)
determine the number of times the PTG module
will write to the AD1CHS0 register.
determine the number of times the PTG module
will write to the AD1CHS0 register.
Work around
Set the PTGPWD<3:0> bits to ‘0000’ so that the
PTG module does not write to the AD1CHS0
register multiple times.
PTG module does not write to the AD1CHS0
register multiple times.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7