Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 232
© 2008 Microchip Technology Inc.
19.4.7
BAUD RATE
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 19-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
SSPxADD register (Figure 19-17). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
‘0’ and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
CY
) on the Q2 and Q4 clocks. In I
2
C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
instruction cycles and the BRG value loaded into
SSPxADD.
19.4.7.1
Baud Rate and Module
Interdependence
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
can operate simultaneously in I
2
C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
FIGURE 19-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 19-3:
I
2
C™ CLOCK RATE w/BRG
SSPM<3:0>
BRG Down Counter
CLKO
F
OSC
/4
SSPxADD<6:0>
SSPM<3:0>
SCLx
Reload
Control
Reload
F
OSC
F
CY
F
CY
*2
BRG Value
F
SCL
(2 Rollovers of BRG)
40 MHz
10 MHz
20 MHz
18h
400 kHz
(1)
40 MHz
10 MHz
20 MHz
1Fh
312.5 kHz
40 MHz
10 MHz
20 MHz
63h
100 kHz
16 MHz
4 MHz
8 MHz
09h
400 kHz
(1)
16 MHz
4 MHz
8 MHz
0Ch
308 kHz
16 MHz
4 MHz
8 MHz
27h
100 kHz
4 MHz
1 MHz
2 MHz
02h
333 kHz
(1)
4 MHz
1 MHz
2 MHz
09h
100 kHz
4 MHz
1 MHz
2 MHz
00h
1 MHz
(1)
Note 1:
The I
2
C interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.