Microchip Technology DV164136 Data Sheet
© 2008 Microchip Technology Inc.
DS39646C-page 233
PIC18F8722 FAMILY
19.4.7.2
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<6:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 19-18).
reloaded with the contents of SSPxADD<6:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 19-18).
FIGURE 19-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx
SCLx
SCLx deasserted but slave holds
DX – 1
DX
BRG
SCLx is sampled high, reload takes
place and BRG starts its count
place and BRG starts its count
03h
02h
01h
00h (hold off)
03h
02h
Reload
BRG
Value
Value
SCLx low (clock arbitration)
SCLx allowed to transition high
BRG decrements on
Q2 and Q4 cycles
Q2 and Q4 cycles