Microchip Technology DV164136 Data Sheet
PIC18F8722 FAMILY
DS39646C-page 318
© 2008 Microchip Technology Inc.
TABLE 25-3:
SUMMARY OF CODE PROTECTION REGISTERS
25.5.1
PROGRAM MEMORY
CODE PROTECTION
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read instruc-
tion that executes from a location outside of that block is
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read instruc-
tion that executes from a location outside of that block is
not allowed to read and will result in reading ‘0’s.
Figures 25-6 through 25-8 illustrate table write and table
read protection.
Figures 25-6 through 25-8 illustrate table write and table
read protection.
FIGURE 25-6:
TABLE WRITE (WRTn) DISALLOWED
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h CONFIG5L
CP7
(1)
CP6
(1)
CP5
(2)
CP4
(2)
CP3
(3)
CP2
CP1
CP0
300009h CONFIG5H
CPD
CPB
—
—
—
—
—
—
30000Ah CONFIG6L
WRT7
(1)
WRT6
(1)
WRT5
(2)
WRT4
(2)
WRT3
(3)
WRT2
WRT1
WRT0
30000Bh CONFIG6H
WRTD
WRTB
WRTC
—
—
—
—
—
30000Ch CONFIG7L EBRT7
(1)
EBRT6
(1)
EBTR5
(2)
EBTR4
(2)
EBTR3
(3)
EBTR2
EBTR1
EBTR0
30000Dh CONFIG7H
—
EBTRB
—
—
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1:
Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set.
2:
Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set.
3:
Unimplemented in PIC18F6527/8527 devices; maintain this bit set.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer. Refer to the device
programming specification for more
information.
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer. Refer to the device
programming specification for more
information.
000000h
0007FFh
000800h
000800h
003FFFh
004000h
004000h
007FFFh
008000h
008000h
00BFFFh
00C000h
00C000h
00FFFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLWT*
TBLPTR = 0008FFh
PC = 003FFEh
TBLWT*
PC = 00BFFEh
Register Values
Program Memory
Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0
.