Microchip Technology DV164136 Data Sheet

DS39646C-page 320

© 2008 Microchip Technology Inc.

25.5.2

DATA EEPROM 
CODE PROTECTION

The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can always read data EEPROM
under normal operation, regardless of the protection bit
settings.

25.5.3

CONFIGURATION REGISTER 
PROTECTION

The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.

Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.

The PIC18F8722 family of devices can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.

When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB

®

 IDE. When the microcontroller has

this feature enabled, some resources are not available
for general use. Table 25-4 shows which resources are
required by the background debugger.

To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to RG5/MCLR/V

PP

, V

DD

,

V

SS

, RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip or one of
the third party development tool companies.

The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
RG5/MCLR/V

PP

 pin, but the RB5/KBI1/PGM pin is then

dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.

While programming, using single-supply programming
mode, V

DD

 is applied to the RG5/MCLR/V

PP

 pin as in

normal execution mode. To enter Programming mode,
V

DD

 is applied to the PGM pin. 

If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V

IHH

 applied to the RG5/

MCLR/V

PP

 pin). Once LVP has been disabled, only the

standard high-voltage programming is available and
must be used to program the device. 

Memory that is not code-protected can be erased using
a block erase, or erased row by row, then written at any
specified V

DD

. If code-protected memory is to be

erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V

DD 

of 4.5V to 5.5V. 

I/O pins:

RB6, RB7

Stack:

2 levels

Program Memory:

512 bytes

Data Memory:

10 bytes

Note 1: High-voltage programming is always

available, regardless of the state of the
LVP bit or the PGM pin, by applying V

IHH

to the MCLR pin.

2: By default, Single-Supply ICSP is

enabled in unprogrammed devices (as
supplied from Microchip) and erased
devices.

3: When Single-Supply Programming is

enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.

4: When LVP is enabled, externally pull the

PGM pin to V

SS

 to allow normal program

execution.