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Microchip Technology DV164136 Data Sheet

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PIC18F87J11 FAMILY
DS39778E-page 112
 
 2007-2012 Microchip Technology Inc.
8.6.4
16-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
 and 
.
FIGURE 8-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED 
MICROCONTROLLER MODE)    
FIGURE 8-5:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED 
MICROCONTROLLER MODE)
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
A<19:16>
ALE
OE
AD<15:0>
CE
Opcode Fetch
Opcode Fetch
Opcode Fetch
TBLRD*
TBLRD
 Cycle 1
ADDLW
 55h
from 000100h
Q2
Q1
Q3
Q4
0Ch
CF33h
TBLRD
 92h
from 199E67h
9256h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD
 Cycle 2
MOVLW
 55h
from 000102h
MOVLW
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
A<19:16>
ALE
OE
3AAAh
AD<15:0>
00h
00h
CE
Opcode Fetch
Opcode Fetch
SLEEP
SLEEP
from 007554h
Q1
Bus Inactive
0003h
3AABh
0E55h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
Sleep Mode, 
MOVLW
 55h
from 007556h