Microchip Technology DV164136 Data Sheet
PIC18F87J11 FAMILY
DS39778E-page 114
2007-2012 Microchip Technology Inc.
8.7.1
8-BIT MODE TIMING
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
and
.
FIGURE 8-7:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
MICROCONTROLLER MODE)
FIGURE 8-8:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED
MICROCONTROLLER MODE)
MICROCONTROLLER MODE)
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
A<19:16>
ALE
OE
AD<7:0>
CE
Opcode Fetch
Opcode Fetch
Opcode Fetch
TBLRD*
TBLRD
Cycle 1
ADDLW
55h
from 000100h
Q2
Q1
Q3
Q4
0Ch
33h
TBLRD
92h
from 199E67h
92h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRD
Cycle 2
MOVLW
55h
from 000102h
MOVLW
AD<15:8>
CFh
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
A<19:16>
ALE
OE
AAh
AD<7:0>
00h
00h
CE
Opcode Fetch
Opcode Fetch
SLEEP
SLEEP
from 007554h
Q1
Bus Inactive
00h
ABh
55h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
Sleep Mode,
MOVLW
55h
from 007556h
AD<15:8>
3Ah
3Ah
03h
0Eh
BA0