Microchip Technology DV164136 Data Sheet
PIC18F87J11 FAMILY
DS39778E-page 152
2007-2012 Microchip Technology Inc.
11.6
PORTE, TRISE and
LATE Registers
LATE Registers
PORTE is an 8-bit wide, bidirectional port. All pins on
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
PORTE are digital only and tolerate voltages up to
5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
On 80-pin devices, PORTE is multiplexed with the
system bus as part of the External Memory Interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
Address/Data bus (AD<15:8>). The TRISE bits are
also overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
system bus as part of the External Memory Interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
Address/Data bus (AD<15:8>). The TRISE bits are
also overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
PORTE is also multiplexed with Enhanced PWM
Outputs B and C for ECCP1 and ECCP3, and
Outputs B, C and D for ECCP2. For all devices, their
default assignments are on PORTE<6:0>. On 80-pin
devices, the multiplexing for the outputs of ECCP1 and
ECCP3 is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For devices operating in Microcontroller mode, the RE7
pin can be configured as the alternate peripheral pin for
the ECCP2 module and Enhanced PWM Output 2A;
this is done by clearing the CCP2MX Configuration bit.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals, PMWR and
PMRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, refer to
Outputs B and C for ECCP1 and ECCP3, and
Outputs B, C and D for ECCP2. For all devices, their
default assignments are on PORTE<6:0>. On 80-pin
devices, the multiplexing for the outputs of ECCP1 and
ECCP3 is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For devices operating in Microcontroller mode, the RE7
pin can be configured as the alternate peripheral pin for
the ECCP2 module and Enhanced PWM Output 2A;
this is done by clearing the CCP2MX Configuration bit.
PORTE is also multiplexed with the Parallel Master
Port address lines. When PMPMX = 0, RE1 and RE0
are multiplexed with the control signals, PMWR and
PMRD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, refer to
EXAMPLE 11-6:
INITIALIZING PORTE
Note:
These pins are configured as digital inputs
on any device Reset.
on any device Reset.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method to clear
; output data latches
MOVLW
03h
; Value used to initialize
; data direction
MOVWF
TRISE
; Set RE<1:0> as inputs
; RE<7:2> as outputs