Microchip Technology DV164136 Data Sheet
PIC18F87J11 FAMILY
DS39778E-page 154
2007-2012 Microchip Technology Inc.
TABLE 11-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE5/AD13/
PMA11/P1C
PMA11/P1C
RE5
0
O
DIG
LATE<5> data output.
1
I
ST
PORTE<5> data input.
AD13
)
x
O
DIG
External Memory Interface, Address/Data Bit 13 output.
(
)
x
I
TTL
External Memory Interface, Data Bit 13 input.
PMA11
x
O
DIG
Parallel Master Port address.
P1C
(
0
O
DIG
ECCP1 Enhanced PWM output, Channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE6/AD14/
PMA10/P1B
PMA10/P1B
RE6
0
O
DIG
LATE<6> data output.
1
I
ST
PORTE<6> data input.
AD14
)
x
O
DIG
External Memory Interface, Address/Data Bit 14 output.
(
)
x
I
TTL
External Memory Interface, Data Bit 14 input.
PMA10
x
O
DIG
Parallel Master Port address.
P1B
(
)
0
O
DIG
ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
PMA9/ECCP2/
P2A
PMA9/ECCP2/
P2A
RE7
0
O
DIG
LATE<7> data output.
1
I
ST
PORTE<7> data input.
AD15
)
x
O
DIG
External Memory Interface, Address/Data Bit 15 output.
(
)
x
I
TTL
External Memory Interface, Data Bit 15 input.
PMA9
x
O
DIG
Parallel Master Port address.
ECCP2
(
0
O
DIG
ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
port data.
1
I
ST
ECCP2 capture input.
P2A
(
)
0
O
DIG
ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
PORTG
RDPU
REPU
RJPU
RG4
RG3
RG2
RG1
RG0
Legend:
Shaded cells are not used by PORTE.
Note 1:
Unimplemented on 64-pin devices, read as ‘0’.
TABLE 11-12: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
Legend:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2:
External Memory Interface I/O takes priority over all other digital and PMP I/O.
3:
Available on 80-pin devices only.
4:
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
5:
Default configuration for PMP (PMPMX Configuration bit = 1).