Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 239
PIC18F87J11 FAMILY
REGISTER 20-1:
SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP:
Sample bit
SPI Master mode:
1
1
= Input data is sampled at the end of data output time
0
= Input data is sampled at the middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE:
SPI Clock Select bit
(
1
= Transmit occurs on transition from the active to Idle clock state
0
= Transmit occurs on transition from the Idle to active clock state
bit 5
D/A:
Data/Address bit
Used in I
2
C™ mode only.
bit 4
P:
Stop bit
Used in I
2
C mode only. This bit is cleared when the MSSPx module is disabled and SSPEN is cleared.
bit 3
S:
Start bit
Used in I
2
C mode only.
bit 2
R/W:
Read/Write Information bit
Used in I
2
C mode only.
bit 1
UA:
Update Address bit
Used in I
2
C mode only.
bit 0
BF:
Buffer Full Status bit (Receive mode only)
1
= Receive is complete, SSPxBUF is full
0
= Receive is not complete, SSPxBUF is empty
Note 1:
The polarity of the clock state is set by the CKP bit (SSPxCON1<4>).