Microchip Technology DV164136 Data Sheet
2007-2012 Microchip Technology Inc.
DS39778E-page 241
PIC18F87J11 FAMILY
20.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a Transmit/Receive
Shift register (SSPxSR) and a Buffer register
(SSPxBUF). The SSPxSR shifts the data in and out of
the device, MSb first. The SSPxBUF holds the data that
was written to the SSPxSR until the received data is
ready. Once the 8 bits of data have been received, that
byte is moved to the SSPxBUF register. Then, the
Buffer Full detect bit, BF (SSPxSTAT<0>), and the
interrupt flag bit, SSPxIF, are set. This double-buffering
of the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL (SSPxCON1<7>), will
be set. User software must clear the WCOL bit so that
it can be determined if the following write(s) to the
SSPxBUF register completed successfully.
• Slave Select mode (Slave mode only)
Each MSSP module consists of a Transmit/Receive
Shift register (SSPxSR) and a Buffer register
(SSPxBUF). The SSPxSR shifts the data in and out of
the device, MSb first. The SSPxBUF holds the data that
was written to the SSPxSR until the received data is
ready. Once the 8 bits of data have been received, that
byte is moved to the SSPxBUF register. Then, the
Buffer Full detect bit, BF (SSPxSTAT<0>), and the
interrupt flag bit, SSPxIF, are set. This double-buffering
of the received data (SSPxBUF) allows the next byte to
start reception before reading the data that was just
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL (SSPxCON1<7>), will
be set. User software must clear the WCOL bit so that
it can be determined if the following write(s) to the
SSPxBUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
shows the
loading of the SSPxBUF (SSPxSR) for data
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
20.3.3
OPEN-DRAIN OUTPUT OPTION
The drivers for the SDOx output and SCKx clock pins
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, and allows the output to communicate with
external circuits without the need for additional level
shifters. For more information, see
can be optionally configured as open-drain outputs.
This feature allows the voltage level on the pin to be
pulled to a higher level through an external pull-up
resistor, and allows the output to communicate with
external circuits without the need for additional level
shifters. For more information, see
.
The open-drain output option is controlled by the
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures the SDOx and SCKx pins for the
corresponding module for open-drain operation.
The ODCON3 register shares the same address as the
T1CON register. The ODCON3 register is accessed by
setting the ADSHR bit in the WDTCON register
(WDTCON<4>).
SPI2OD and SPI1OD bits (ODCON3<1:0>). Setting an
SPIxOD bit configures the SDOx and SCKx pins for the
corresponding module for open-drain operation.
The ODCON3 register shares the same address as the
T1CON register. The ODCON3 register is accessed by
setting the ADSHR bit in the WDTCON register
(WDTCON<4>).
EXAMPLE 20-1:
LOADING THE SSP1BUF (SSP1SR) REGISTER
LOOP
BTFSS
SSP1STAT, BF
;Has data been received (transmit complete)?
BRA
LOOP
;No
MOVF
SSP1BUF, W
;WREG reg = contents of SSP1BUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
TXDATA, W
;W reg = contents of TXDATA
MOVWF
SSP1BUF
;New data to xmit