Microchip Technology MA330018 Data Sheet
© 2007-2012 Microchip Technology Inc.
DS70291G-page 441
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Revision C (May 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of V
DDCORE
and V
DDCORE
/
V
CAP
to V
CAP
/V
DDCORE
The other changes are referenced by their respective
section in the following table.
section in the following table.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit Digital
Signal Controllers”
Signal Controllers”
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to V
references pin connections to V
SS
.
Section 1.0 “Device Overview”
Updated AV
DD
in the PINOUT I/O Descriptions (see Table 1-1).
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Started with 16-bit Digital Signal
Controllers”
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
started with 16-bit Digital Signal Controllers.
Section 3.0 “CPU”
Updated CPU Core Block Diagram with a connection from the DSP Engine
to the Y Data Bus (see Figure 3-1).
to the Y Data Bus (see Figure 3-1).
Vertically extended the X and Y Data Bus lines in the DSP Engine Block
Diagram (see Figure 3-3).
Diagram (see Figure 3-3).
Section 4.0 “Memory Organization” Updated Reset value for CORCON in the CPU Core Register Map (see
Table 4-1).
Removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register Map
(see Table 4-4).
(see Table 4-4).
Updated bit locations for RPINR25 in the Peripheral Pin Select Input
Register Map (see Table 4-24).
Register Map (see Table 4-24).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-36).
(see Table 4-36).
Section 5.0 “Flash Program
Memory”
Memory”
Updated Section 5.3 “Programming Operations” with programming time
formula.
formula.
Section 9.0 “Oscillator
Configuration”
Configuration”
Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock Sources”.
“System Clock Sources”.
Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
Register 9-4).
Section 10.0 “Power-Saving
Features”
Features”
Added the following registers:
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)