Microchip Technology MA320002 Data Sheet
©
2011 Micr
och
ip T
e
e
chn
o
logy Inc.
D
S
6
1143H-p
age 69
PIC32MX3XX/4XX
TABLE 4-19:
FLASH CONTROLLER REGISTERS MAP
V
irtual A
ddress
(BF80_#
)
Regis
ter
Na
m
e
Bit Range
Bits
All
R
e
set
s
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F400 NVMCON
(1)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
WR
WREN
WRERR
LVDERR
LVDSTAT
—
—
—
—
—
—
—
NVMOP<3:0>
0000
F410
NVMKEY
31:16
NVMKEY<31:0>
0000
15:0
0000
F420
NVMADDR
(1)
31:16
NVMADDR<31:0>
0000
15:0
0000
F430
NVMDATA
31:16
NVMDATA<31:0>
0000
15:0
0000
F440
NVMSRC
ADDR
31:16
NVMSRCADDR<31:0>
0000
15:0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
for more information.
TABLE 4-20:
SYSTEM CONTROL REGISTERS MAP
(1,2)
V
ir
tual
Addr
es
s
(B
F80
_#)
Re
g
iste
r
Name
Bit R
a
n
g
e
Bits
All Rese
ts
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F000 OSCCON
31:16
—
—
PLLODIV<2:0>
FRCDIV<2:0>
—
SOSCRDY
—
PBDIV<1:0>
PLLMULT<2:0>
0000
15:0
—
COSC<2:0>
—
NOSC<2:0>
CLKLOCK
ULOCK
SLOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
0000
F010
OSCTUN
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
TUN<5:0>
0000
0000 WDTCON
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
—
—
—
—
—
—
—
—
SWDTPS<4:0>
—
WDTCLR 0000
F600
RCON
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CMR
VREGS
EXTR
SWR
—
WDTO
SLEEP
IDLE
BOR
POR
0000
F610
RSWRST
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST
0000
F230 SYSKEY
(3)
31:16
SYSKEY<31:0>
0000
15:0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
for more information.
2:
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
3:
This register does not have associated CLR, SET, and INV registers.