Microchip Technology MA320002 Data Sheet

PIC32MX3XX/4XX

DS61143H

-page 70

2011 Microchip T

chnolo

y Inc.

TABLE 4-21:

PORTA REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6000

TRISA

31:16

—

0000

15:0

TRISA15

TRISA14

—

TRISA10

TRISA9

—

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

C6FF

6010

PORTA

31:16

—

0000

15:0

RA15

RA14

—

RA10

RA9

—

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xxxx

6020

LATA

31:16

—

0000

15:0

LATA15

LATA14

—

LATA10

LATA9

—

LATA7

LATA6

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

xxxx

6030

ODCA

31:16

—

0000

15:0

ODCA15

ODCA14

—

ODCA10

ODCA9

—

ODCA7

ODCA6

ODCA5

ODCA4

ODCA3

ODCA2

ODCA1

ODCA0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-22:

PORTB REGISTERS MAP

(1)

irtual Address

(BF88_#

)

Regis

ter

Name

Bit Range

Bits

All Re

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6040

TRISB

31:16

—

0000

15:0

TRISB15

TRISB14

TRISB13

TRISB12

TRISB11

TRISB10

TRISB9

TRISB8

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

FFFF

6050

PORTB

31:16

—

0000

15:0

RB15

RB14

RB13

RB12

RB11

RB10

RB9

RB8

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx

6060

LATB

31:16

—

0000

15:0

LATB15

LATB14

LATB13

LATB12

LATB11

LATB10

LATB9

LATB8

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2

LATB1

LATB0

xxxx

6070

ODCB

31:16

—

0000

15:0

ODCB15

ODCB14

ODCB13

ODCB12

ODCB11

ODCB10

ODCB9

ODCB8

ODCB7

ODCB6

ODCB5

ODCB4

ODCB3

ODCB2

ODCB1

ODCB0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.