Microchip Technology MA320002 Data Sheet

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 71

PIC32MX3XX/4XX

TABLE 4-23:

PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6080

TRISC

31:16

—

0000

15:0

TRISC15

TRISC14

TRISC13

TRISC12

—

TRISC4

TRISC3

TRISC2

TRISC1

—

F01E

6090

PORTC

31:16

—

0000

15:0

RC15

RC14

RC13

RC12

—

RC4

RC3

RC2

RC1

—

xxxx

60A0

LATC

31:16

—

0000

15:0

LATC15

LATC14

LATC13

LATC12

—

LATC4

LATC3

LATC2

LATC1

—

xxxx

60B0

ODCC

31:16

—

0000

15:0

ODCC15

ODCC14

ODCC13

ODCC12

—

ODCC4

ODCC3

ODCC2

ODCC1

—

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-24:

PORTC REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY

(1)

irtual Address

(BF88_#

)

Regis

ter

Name

it Range

Bits

All Re

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6080

TRISC

31:16

—

0000

15:0

TRISC15

TRISC14

TRISC13

TRISC12

—

F000

6090

PORTC

31:16

—

0000

15:0

RC15

RC14

RC13

RC12

—

xxxx

60A0

LATC

31:16

—

0000

15:0

LATC15

LATC14

LATC13

LATC12

—

xxxx

60B0

ODCC

31:16

—

0000

15:0

ODCC15

ODCC14

ODCC13

ODCC12

—

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.