Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 230
2011-2013 Microchip Technology Inc.
16.3
PWMx Control Registers
REGISTER 16-1:
PTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0
U-0
R/W-0
HS/HC-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
—
PTSIDL
SESTAT
SEIEN
EIPU
)
SYNCPOL
)
SYNCOEN
)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCEN
(
)
SYNCSRC2
)
SYNCSRC1
(
SYNCSRC0
SEVTPS3
)
SEVTPS2
SEVTPS1
)
SEVTPS0
)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PTEN:
PWMx Module Enable bit
1
= PWMx module is enabled
0
= PWMx module is disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
PTSIDL:
PWMx Time Base Stop in Idle Mode bit
1
= PWMx time base halts in CPU Idle mode
0
= PWMx time base runs in CPU Idle mode
bit 12
SESTAT:
Special Event Interrupt Status bit
1
= Special event interrupt is pending
0
= Special event interrupt is not pending
bit 11
SEIEN:
Special Event Interrupt Enable bit
1
= Special event interrupt is enabled
0
= Special event interrupt is disabled
bit 10
EIPU:
Enable Immediate Period Updates bit
1
= Active Period register is updated immediately
0
= Active Period register updates occur on PWMx cycle boundaries
bit 9
SYNCPOL:
Synchronize Input and Output Polarity bit
(
)
1
= SYNCI1/SYNCO1 polarity is inverted (active-low)
0
= SYNCI1/SYNCO1 is active-high
bit 8
SYNCOEN:
Primary Time Base Sync Enable bit
(
1
= SYNCO1 output is enabled
0
= SYNCO1 output is disabled
bit 7
SYNCEN:
External Time Base Synchronization Enable bit
1
= External synchronization of primary time base is enabled
0
= External synchronization of primary time base is disabled
Note 1:
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2:
See
for information on this selection.