Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 232
2011-2013 Microchip Technology Inc.
REGISTER 16-2:
PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCLKDIV2
(
PCLKDIV1
)
PCLKDIV0
(
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented:
Read as ‘0’
bit 2-0
PCLKDIV<2:0>:
PWMx Input Clock Prescaler (Divider) Select bits
)
111
= Reserved
110
= Divide-by-64
101
= Divide-by-32
100
= Divide-by-16
011
= Divide-by-8
010
= Divide-by-4
001
= Divide-by-2
000
= Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
yield unpredictable results.