Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 231
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6-4
SYNCSRC<2:0>:
Synchronous Source Selection bits
(
)
111
= Reserved
•
•
•
100
•
•
100
= Reserved
011
= PTGO17
(
)
010
= PTGO16
(
)
001
= Reserved
000
= SYNCI1 input from PPS
bit 3-0
SEVTPS<3:0>:
PWMx Special Event Trigger Output Postscaler Select bits
(
)
1111
= 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
•
•
•
0001
•
•
0001
= 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000
= 1:1 Postscaler generates Special Event Trigger on every compare match event
REGISTER 16-1:
PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
Note 1:
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2:
See
Section 24.0 “Peripheral Trigger Generator (PTG) Module”
for information on this selection.