Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 264
© 2009 Microchip Technology Inc.
20.4.2
EUSART SYNCHRONOUS SLAVE
RECEPTION
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the chip from the low-
power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the chip from the low-
power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1.
1.
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2.
If interrupts are desired, set enable bit, RCIE.
3.
If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
4.
If 9-bit reception is desired, set bit, RX9.
5.
To enable reception, set enable bit, CREN.
6.
Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
complete. An interrupt will be generated if
enable bit, RCIE, was set.
7.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
8.
Read the 8-bit received data by reading the
RCREG register.
RCREG register.
9.
If any error occurred, clear the error by clearing
bit, CREN.
bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
set.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
SPPIF
(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
SPPIE
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
SPPIP
(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG
EUSART Receive Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH
EUSART Baud Rate Generator Register High Byte
SPBRG
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.