Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 266
© 2009 Microchip Technology Inc.
REGISTER 21-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
(1)
R/W
(1)
R/W
(1)
R/W
(1)
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
VCFG1: Voltage Reference Configuration bit (V
REF
- source)
1 = V
REF
- (AN2)
0 = V
SS
bit 4
VCFG0: Voltage Reference Configuration bit (V
REF
+ source)
1 = V
REF
+ (AN3)
0 = V
DD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1:
The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2:
AN5 through AN7 are available only on 40/44-pin devices.
A = Analog input
D = Digital I/O
PCFG3:
PCFG0
AN1
2
AN1
1
AN1
0
AN9
AN8
AN7
(2
)
AN6
(2
)
AN5
(2
)
AN4
AN3
AN2
AN1
AN0
0000
(1)
A
A
A
A
A
A
A
A
A
A
A
A
A
0001
A
A
A
A
A
A
A
A
A
A
A
A
A
0010
A
A
A
A
A
A
A
A
A
A
A
A
A
0011
D
A
A
A
A
A
A
A
A
A
A
A
A
0100
D
D
A
A
A
A
A
A
A
A
A
A
A
0101
D
D
D
A
A
A
A
A
A
A
A
A
A
0110
D
D
D
D
A
A
A
A
A
A
A
A
A
0111
(1)
D
D
D
D
D
A
A
A
A
A
A
A
A
1000
D
D
D
D
D
D
A
A
A
A
A
A
A
1001
D
D
D
D
D
D
D
A
A
A
A
A
A
1010
D
D
D
D
D
D
D
D
A
A
A
A
A
1011
D
D
D
D
D
D
D
D
D
A
A
A
A
1100
D
D
D
D
D
D
D
D
D
D
A
A
A
1101
D
D
D
D
D
D
D
D
D
D
D
A
A
1110
D
D
D
D
D
D
D
D
D
D
D
D
A
1111
D
D
D
D
D
D
D
D
D
D
D
D
D