Microchip Technology AC164139 Data Sheet
2010 Microchip Technology Inc.
DS39969B-page 149
PIC24FJ256DA210 FAMILY
A recommended code sequence for a clock switch
includes the following:
1.
includes the following:
1.
Disable interrupts during the OSCCON register
unlock and write sequence.
unlock and write sequence.
2.
Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back
instructions.
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back
instructions.
3.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
the instruction immediately following the unlock
sequence.
4.
Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
5.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
following the unlock sequence.
6.
Continue to execute code that is not
clock-sensitive (optional).
clock-sensitive (optional).
7.
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 8-1.
and initiating a clock switch is shown in Example 8-1.
EXAMPLE 8-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
IN ASSEMBLY
FOR CLOCK SWITCHING
IN ASSEMBLY
8.5
96 MHz PLL Block
The 96 MHz PLL block is implemented to generate the
stable 48 MHz clock required for full-speed USB
operation, a programmable clock output for the
graphics controller module and the system clock from
the same oscillator source. The 96 MHz PLL block is
shown in Figure 8-2.
The 96 MHz PLL block requires a 4 MHz input signal; it
uses this to generate a 96 MHz signal from a fixed, 24x
PLL. This is, in turn, divided into three branches. The first
branch generates the USB clock, the second branch
generates the system clock and the third branch gener-
ates the graphics clock. The 96 MHz PLL block can be
enabled and disabled using the PLL96MHZ Configura-
tion bit (Configuration Word<11>) or through the PLLEN
(CLKDIV<5>) control bit when the PLL96MHZ
Configuration bit is not set. Note that the PLL96MHZ
Configuration bit and PLLEN register bit are available
only for PIC24F devices with USB and graphics
controller modules.
The 96 MHz PLL prescaler does not automatically
sense the incoming oscillator frequency. The user must
manually configure the PLL divider to generate the
required 4 MHz output, using the PLLDIV<2:0> Config-
uration bits (Configuration Word 2<14:12> in most
devices).
stable 48 MHz clock required for full-speed USB
operation, a programmable clock output for the
graphics controller module and the system clock from
the same oscillator source. The 96 MHz PLL block is
shown in Figure 8-2.
The 96 MHz PLL block requires a 4 MHz input signal; it
uses this to generate a 96 MHz signal from a fixed, 24x
PLL. This is, in turn, divided into three branches. The first
branch generates the USB clock, the second branch
generates the system clock and the third branch gener-
ates the graphics clock. The 96 MHz PLL block can be
enabled and disabled using the PLL96MHZ Configura-
tion bit (Configuration Word<11>) or through the PLLEN
(CLKDIV<5>) control bit when the PLL96MHZ
Configuration bit is not set. Note that the PLL96MHZ
Configuration bit and PLLEN register bit are available
only for PIC24F devices with USB and graphics
controller modules.
The 96 MHz PLL prescaler does not automatically
sense the incoming oscillator frequency. The user must
manually configure the PLL divider to generate the
required 4 MHz output, using the PLLDIV<2:0> Config-
uration bits (Configuration Word 2<14:12> in most
devices).
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV #OSCCONH,
w1
MOV #0x78,
w2
MOV #0x9A,
w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Set new oscillator selection
MOV.b WREG,
OSCCONH
;OSCCONL (low byte) unlock sequence
MOV #OSCCONL,
w1
MOV #0x46,
w2
MOV #0x57,
w3
MOV.b w2,
[w1]
MOV.b w3,
[w1]
;Start oscillator switch operation
BSET OSCCON,#0