Microchip Technology AC164139 Data Sheet
PIC24FJ256DA210 FAMILY
DS39969B-page 150
2010 Microchip Technology Inc.
FIGURE 8-2:
96 MHz PLL BLOCK
8.5.1
SYSTEM CLOCK GENERATION
The system clock is generated from the 96 MHz branch
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
as the system clock. Figure 8-2 shows this logic in the
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
TABLE 8-2:
SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK
96 MHz
PLL
P
LL P
resc
a
ler
PLLDIV<2:0>
Input from
POSC
Input from
FRC
÷12
÷ 8
÷ 6
÷ 8
÷ 6
÷ 3
÷ 2
÷ 1
÷ 1
111
110
101
100
011
010
001
000
110
101
100
011
010
001
000
FNOSC<2:0>
÷ 3
48 MHz Clock
for USB Module
P
o
st
sc
a
le
r
÷ 64
÷ 63
...
÷ 17.50
÷ 17.00
÷ 63
...
÷ 17.50
÷ 17.00
...
÷ 1.25
÷ 1
÷ 1
127
126
...
65
64
...
1
0
GCLKDIV<6:0>
Clock Output for
Display Interface
(DISPCLK)
÷ 2
0
1
Clock Output
for Graphics
Controller
Module (G1CLK)
G1CLKSEL
Graphics Clock
Option 2
Post
scal
er
CPDIV<1:0>
÷ 8
÷ 4
÷ 2
÷ 1
÷ 4
÷ 2
÷ 1
11
10
01
00
10
01
00
PLL Output for
System Clock
4 MHz or
8 MHz
96 MHz Branch
96 MHz PLL
USB Clock
.
.
.
Graphics Clock
System Clock
4 MHz Branch
Graphics Clock
Option 1
48 MHz Branch
÷ 2
÷ 4
÷ 5
MCU Clock Division
(CPDIV<1:0>)
System Clock Frequency
(Instruction Rate in MIPS)
None (00)
32 MHz (16)
2 (01)
16 MHz (8)
4 (10)
8 MHz (4)
(1)
8 (11)
4 MHz (2)
(1)
Note 1:
These options are not compatible with USB operation. They may be used whenever the PLL branch is
selected and the USB module is disabled.
selected and the USB module is disabled.