Microchip Technology 25AA512-I/SN Memory IC SOIC-8 25AA512-I/SN Data Sheet
Product codes
25AA512-I/SN
2010 Microchip Technology Inc.
DS22021F-page 13
25AA512
2.5
Write Status Register Instruction
(WRSR)
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
ARRAY PROTECTION
FIGURE 2-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1
BP0
Array Addresses
Write-Protected
Array Addresses
Unprotected
0
0
none
All (Sectors 0, 1, 2 & 3)
(0000h-FFFFh)
0
1
Upper 1/4 (Sector 3)
(C000h-FFFFh)
Lower 3/4 (Sectors 0, 1 & 2)
(0000h-BFFFh)
1
0
Upper 1/2 (Sectors 2 & 3)
(8000h-FFFFh)
Lower 1/2 (Sectors 0 & 1)
(0000h-7FFFh)
1
1
All (Sectors 0, 1, 2 & 3)
(0000h-FFFFh)
none
SO
SI
CS
9
10
11
12
13
14
15
0
1
0
0
0
0
0
0
7
6
5
4
2
1
0
Instruction
Data to STATUS Register
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
3