Microchip Technology 25AA512-I/SN Memory IC SOIC-8 25AA512-I/SN Data Sheet

DS22021F-page 14

 2010 Microchip Technology Inc.

The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set 

the write enable latch

• After a byte write, page write or STATUS register 

write, the write enable latch is reset

• CS must be set high after the proper number of 

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle 

is ignored and programming is continued

The 25AA512 powers on in the following state:
• The device is in low-power Standby mode 

(CS = 1)

• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to 

enter active state

0

x

x

Protected

Protected

Protected

1

0

x

Protected

Writable

Writable

1

1

0 (low)

Protected

Writable

Protected

1

1

1 (high)

Protected

Writable

Writable

x = don’t care