STMicroelectronics M93C66-WMN6P Memory IC M93C66-WMN6P Data Sheet
Product codes
M93C66-WMN6P
DocID4997 Rev 15
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x
READY/BUSY status
32
6 READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t
SLSH
, before this status information
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).