STMicroelectronics M93C66-WMN6P Memory IC User Manuals

Table of Contents

• Table 1. Device summary

  1
• 1 Description

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  • Table 2. Memory size versus organization

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  • Figure 1. Logic diagram

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  • Table 3. Signal names

    6
  • Figure 2. 8-pin package connections (top view)

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• 2 Connecting to the serial bus

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  • Figure 3. Bus master and memory devices on the serial bus

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• 3 Operating features

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  • 3.1 Supply voltage (VCC)

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    • 3.1.1 Operating supply voltage (VCC)

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    • 3.1.2 Power-up conditions

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    • 3.1.3 Power-up and device reset

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    • 3.1.4 Power-down

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• 4 Memory organization

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  • Figure 4. M93Cx6 ORG input connection

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• 5 Instructions

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  • Table 4. Instruction set for the M93C46

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  • Table 5. Instruction set for the M93C56 and M93C66

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  • Table 6. Instruction set for the M93C76 and M93C86

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  • 5.1 Read Data from Memory

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  • 5.2 Erase and Write data

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    • 5.2.1 Write Enable and Write Disable

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    • 5.2.2 Write

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      • Figure 5. READ, WRITE, WEN, WDS sequences

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    • 5.2.3 Write All

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      • Figure 6. WRAL sequence

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    • 5.2.4 Erase Byte or Word

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      • Figure 7. ERASE, ERAL sequences

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    • 5.2.5 Erase All

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• 6 READY/BUSY status

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• 7 Initial delivery state

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• 8 Clock pulse counter

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  • Figure 8. Write sequence with one clock glitch

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• 9 Maximum ratings

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  • Table 7. Absolute maximum ratings

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• 10 DC and AC parameters

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  • Table 8. Operating conditions (M93Cx6-W)

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  • Table 9. Operating conditions (M93Cx6-R)

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  • Table 10. Cycling performance

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  • Table 11. Memory cell data retention

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  • Table 12. AC measurement conditions

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  • Figure 9. AC testing input output waveforms

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  • Table 13. Input and output capacitance

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  • Table 14. DC characteristics (M93Cx6-W, device grade 6)

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  • Table 15. DC characteristics (M93Cx6-R)

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  • Table 16. AC characteristics (M93Cx6-W, M93Cx6-R, device grade 6)

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  • Table 17. AC characteristics (M93Cx6-R)

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  • Figure 10. Synchronous timing (Start and op-code input)

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  • Figure 11. Synchronous timing (Read)

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  • Figure 12. Synchronous timing (Write)

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• 11 Package mechanical data

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  • Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package outline

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  • Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package mechanical data

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  • Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline

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  • Table 19. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data

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  • Figure 15. UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3 mm, outline

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  • Table 20. UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead x 3 mm, data

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  • Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline

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  • Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

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• 12 Part numbering

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  • Table 22. Ordering information scheme

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• 13 Revision history

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  • Table 23. Document revision history

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