Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 123
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
EXAMPLE 4-2:
EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION
The paged memory scheme provides access to
multiple 32-Kbyte windows in the EDS and PSV
memory. The Data Space Page registers DSxPAG, in
combination with the upper half of data space address
can provide up to 16 Mbytes of additional address
space in the EDS and 12 Mbytes (DSRPAG only) of
PSV address space. The paged data memory space is
shown in
multiple 32-Kbyte windows in the EDS and PSV
memory. The Data Space Page registers DSxPAG, in
combination with the upper half of data space address
can provide up to 16 Mbytes of additional address
space in the EDS and 12 Mbytes (DSRPAG only) of
PSV address space. The paged data memory space is
shown in
The Program Space (PS) can be accessed with
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG. Writes to PS are not
supported, so DSWPAG is dedicated to DS, including
EDS, only. The data space and EDS can be read from
and written to using DSRPAG and DSWPAG,
respectively.
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG. Writes to PS are not
supported, so DSWPAG is dedicated to DS, including
EDS, only. The data space and EDS can be read from
and written to using DSRPAG and DSWPAG,
respectively.
1
DSWPAG<8:0>
9 Bits
EA
15 Bits
Byte
24-Bit EDS EA
Select
EA
(DSWPAG = Don’t Care)
No EDS Access
Select
16-Bit DS EA
Byte
EA<15> = 0
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Generate
PSV Address
0
EA<15>