Microchip Technology MA330025-1 Data Sheet

DS70616G-page 138

 2009-2012 Microchip Technology Inc.

 

R/SO-0

R/W-0

R/W-0

R/W-0

U-0

U-0

U-0

U-0

WR

WREN

WRERR

NVMSIDL

—

—

—

—

bit 15

bit 8

U-0

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

—

—

NVMOP<3:0>

bit 7

bit 0

SO = Settable Only bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

WR: Write Control bit

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is

cleared by hardware once operation is complete

0 = Program or erase operation is complete and inactive

bit 14

WREN: Write Enable bit

1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations

bit 13

WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12

NVMSIDL: NVM Stop-in-Idle Control bit

1 = Flash voltage regulator goes into Stand-by mode during Idle mode
0 = Flash voltage regulator is active during Idle mode

bit 11-4

Unimplemented: Read as ‘0’

bit 3-0

NVMOP<3:0>: NVM Operation Select bits

1111 = Reserved
1110 = Reserved
1101 = Bulk erase primary program Flash memory
1100 = Reserved
1011 = Reserved
1010 = Bulk erase auxiliary program Flash memory
0011 = Memory page erase operation
0010 = Memory row program operation
0001 = Memory word program operation

0000 = Program a single Configuration register byte

Note 1: These bits can only be reset on a POR.

2: If this bit is set, upon exiting Idle mode, there is a delay (T

VREG

) before Flash memory becomes 

operational.

3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words are programmed during execution of this operation.