Microchip Technology MA330025-1 Data Sheet

 2009-2012 Microchip Technology Inc.

DS70616G-page 141

The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset 
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset 
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset

A simplified block diagram of the Reset module is
shown in 

Any active source of Reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 8. “Reset”
(DS70602) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(

www.microchip.com

).

2: Some registers and associated bits

described in this section may not be
available on all devices. Refer to

 in

this data sheet for device-specific register
and bit information.

Refer to the specific peripheral section or

 of

this manual for register Reset states.

MCLR

V

DD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

V

DD

 Rise

Detect

POR

Configuration Mismatch

Security Reset