Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 341
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 18-2:
SPI
X
CON1: SPI
X
CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN
CKP
MSTEN
SPRE<2:0>
PPRE<1:0>
(
)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx Pin bit (SPIx Master modes only)
1 = Internal SPIx clock is disabled, pin functions as I/O
0 = Internal SPIx clock is enabled
1 = Internal SPIx clock is disabled, pin functions as I/O
0 = Internal SPIx clock is enabled
bit 11
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
(
)
Master mode:
1 = Input data is sampled at end of data output time
0 = Input data is sampled at middle of data output time
Slave mode:
The SMP bit must be cleared when SPIx module is used in Slave mode.
1 = Input data is sampled at end of data output time
0 = Input data is sampled at middle of data output time
Slave mode:
The SMP bit must be cleared when SPIx module is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit
(
)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7
SSEN: Slave Select Enable bit (Slave mode)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by module, pin is controlled by port function
0 = SSx pin is not used by module, pin is controlled by port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in the Framed SPIx modes. Program this bit to ‘0’ for Framed SPIx modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to a value of 1:1.
4: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0.
3: Do not set both primary and secondary prescalers to a value of 1:1.
4: The SMP bit must be set only after setting the MSTEN bit. The SMP bit remains cleared if MSTEN = 0.