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Microchip Technology MA330025-1 Data Sheet

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dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 346
 2009-2012 Microchip Technology Inc.
FIGURE 19-1:
I
2
C™ BLOCK DIAGRAM   (
X
 = 1 OR 2) 
Internal
Data Bus
SCLx/
SDAx/
Shift
Match Detect
I2CxADD
Start and Stop
Bit Detect
Clock
Address Match
Clock
Stretching
I2CxTRN
LSb
Shift Clock
BRG Down Counter
F
P
Start and Stop
Bit Generation
Acknowledge
Generation
Collision
Detect
I2CxCON
I2CxSTAT
Co
ntrol Logic
Read
LSb
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxRCV
ASDAx
(1)
ASDLx
(1)
Note 1:
The availability of I
2
C interfaces varies by device. Refer to the 
 section for availability. 
Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and 
ALTI2C2 (FPOR<5:4>). See 
 for more information.
Reload
Control
I2CxMSK