Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 37
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
3.0
CPU
The CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including
significant support for digital signal processing. The
CPU has a 24-bit instruction word, with a variable
length opcode field. The Program Counter (PC) is
24 bits wide and addresses up to 4M x 24 bits of user
program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
architecture with an enhanced instruction set, including
significant support for digital signal processing. The
CPU has a 24-bit instruction word, with a variable
length opcode field. The Program Counter (PC) is
24 bits wide and addresses up to 4M x 24 bits of user
program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1
Registers
Devices have sixteen 16-bit working registers in the
programmer’s model. Each of the working registers
can act as a Data, Address or Address Offset register.
The 16th working register (W15) operates as a Soft-
ware Stack Pointer for interrupts and calls. The working
registers, W0 through W3, and selected bits from the
STATUS register, have shadow registers for fast
context saves and restores using a single POP.S or
PUSH.S instruction.
programmer’s model. Each of the working registers
can act as a Data, Address or Address Offset register.
The 16th working register (W15) operates as a Soft-
ware Stack Pointer for interrupts and calls. The working
registers, W0 through W3, and selected bits from the
STATUS register, have shadow registers for fast
context saves and restores using a single POP.S or
PUSH.S instruction.
3.2
Instruction Set
The dsPIC33EPXXXMU806/810/814 instruction set
has two classes of instructions: the MCU class of
instructions and the DSP class of instructions. The
PIC24EPXXX(GP/GU)810/814 instruction set has the
MCU class of instructions and does not support DSP
instructions. These two instruction classes are seam-
lessly integrated into the architecture and execute from
a single execution unit. The instruction set includes
many addressing modes and was designed for
optimum C compiler efficiency.
has two classes of instructions: the MCU class of
instructions and the DSP class of instructions. The
PIC24EPXXX(GP/GU)810/814 instruction set has the
MCU class of instructions and does not support DSP
instructions. These two instruction classes are seam-
lessly integrated into the architecture and execute from
a single execution unit. The instruction set includes
many addressing modes and was designed for
optimum C compiler efficiency.
3.3
Data Space Addressing
The Base Data Space can be addressed as 32K words
or 64 Kbytes and is split into two blocks, referred to as
X and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. On dsPIC33EPXXX(GP/MC/
MU)806/810/814 devices, certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into Program Space at any
16K program word boundary. The program-to-data
space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access Program
Space as if it were data space. Moreover, the Base
Data Space address is used in conjunction with a read
or write page register (DSRPAG or DSWPAG) to form
an Extended Data Space (EDS) address. The EDS can
be addressed as 8M words or 16 Mbytes. Refer to
Section 3. “Data Memory” (DS70595) and Section 4.
“Program Memory” (DS70613) in the “dsPIC33E/
PIC24E Family Reference Manual” for more details on
EDS, PSV and table accesses.
On dsPIC33EPXXX(GP/MC/MU)806/810/814 devices,
overhead-free circular buffers (Modulo Addressing) are
supported in both X and Y address spaces. The
Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. The X AGU
circular addressing can be used with any of the MCU
class of instructions. The X AGU also supports Bit-
Reversed Addressing to greatly simplify input or output
data reordering for radix-2 FFT algorithms.
PIC24EPXXX(GP/GU)810/814 devices do not support
Modulo and Bit-Reversed Addressing.
or 64 Kbytes and is split into two blocks, referred to as
X and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. On dsPIC33EPXXX(GP/MC/
MU)806/810/814 devices, certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into Program Space at any
16K program word boundary. The program-to-data
space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access Program
Space as if it were data space. Moreover, the Base
Data Space address is used in conjunction with a read
or write page register (DSRPAG or DSWPAG) to form
an Extended Data Space (EDS) address. The EDS can
be addressed as 8M words or 16 Mbytes. Refer to
Section 3. “Data Memory” (DS70595) and Section 4.
“Program Memory” (DS70613) in the “dsPIC33E/
PIC24E Family Reference Manual” for more details on
EDS, PSV and table accesses.
On dsPIC33EPXXX(GP/MC/MU)806/810/814 devices,
overhead-free circular buffers (Modulo Addressing) are
supported in both X and Y address spaces. The
Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. The X AGU
circular addressing can be used with any of the MCU
class of instructions. The X AGU also supports Bit-
Reversed Addressing to greatly simplify input or output
data reordering for radix-2 FFT algorithms.
PIC24EPXXX(GP/GU)810/814 devices do not support
Modulo and Bit-Reversed Addressing.
3.4
Addressing Modes
The CPU supports these addressing modes:
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 2. “CPU”
(DS70359) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 2. “CPU”
(DS70359) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.