Microchip Technology MA330025-1 Data Sheet

 2009-2012 Microchip Technology Inc.

DS70616G-page 407

U-0

U-0

U-0

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

—

—

—

bit 15

bit 8

R/W-0

R/W-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LSPD

RETRYDIS

—

EPCONDIS

EPRXEN

EPTXEN

EPSTALL

EPHSHK

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

Unimplemented: Read as ‘0’

bit 7

LSPD: Low-Speed Direct Connection Enable bit (UEP0 only)

1 = Direct connection to a low-speed device is enabled
0 = Direct connection to a low-speed device is disabled

bit 6

RETRYDIS: Retry Disable bit (UEP0 only)

1 = Retry NAK transactions is disabled
0 = Retry NAK transactions is enabled; retry done in hardware

bit 5

Unimplemented: Read as ‘0’

bit 4

EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN and EPRXEN = 1:
1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed
0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed
For all other combinations of EPTXEN and EPRXEN:
This bit is ignored.

bit 3

EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive is enabled
0 = Endpoint n receive is disabled

bit 2

EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit is enabled
0 = Endpoint n transmit is disabled

bit 1

EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled

bit 0

EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake is enabled
0 = Endpoint handshake is disabled (typically used for isochronous endpoints)

Note 1: These bits are available only for UxEP0 and only in Host mode. For all other UxEPn registers, these bits 

are always unimplemented and read as ‘0’.