Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 445
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 25-4:
CMxMSKCON: COMPARATOR x MASK GATING
CONTROL REGISTER
CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HLMS: High or Low-Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14
Unimplemented: Read as '0'
bit 13
OCEN: OR Gate C Input Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11
OBEN: OR Gate B Input Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7
NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6
PAGS: AND Gate Output Enable bit
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5
ACEN: AND Gate C Input Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4
ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate