Microchip Technology MA330025-1 Data Sheet

DS70616G-page 452

 2009-2012 Microchip Technology Inc.

R/W-0

U-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

RTCEN

—

RTCWREN

RTCSYNC HALFSEC

RTCOE

RTCPTR<1:0>

bit 15

bit 8

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

CAL<7:0>

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

RTCEN: RTCC Enable bit

1 = RTCC module is enabled
0 = RTCC module is disabled

bit 14

Unimplemented: Read as ‘0’

bit 13

RTCWREN: RTCC Value Registers Write Enable bit 
1 = RTCVAL register can be written to by the user application
0 = RTCVAL register is locked out from being written to by the user application

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = A rollover is about to occur in 32 clock edges (approximately 1 ms)
0 = A rollover will not occur

bit 11

HALFSEC: Half-Second Status bit

1 = Second half period of a second
0 = First half period of a second

bit 10

RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled

bit 9-8

RTCPTR<1:0>: RTCC Value Register Pointer bits
Points to the corresponding RTCC Value register when reading the RTCVAL register; the
RTCPTR<1:0> value decrements on every access of the RTCVAL register until it reaches ‘00’.

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written.