Microchip Technology MA330025-1 Data Sheet

 2009-2012 Microchip Technology Inc.

DS70616G-page 467

The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable. 
Key features of the PMP module include:
• Eight Data Lines
• Up to 16 Programmable Address Lines
• Up to 2 Chip Select Lines
• Programmable Strobe Options:

- Individual read and write strobes, or
- Read/Write strobe with enable strobe

• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port (PSP) Support
• Enhanced Parallel Slave Support:

- Address support
- 4-byte deep auto-incrementing buffer

• Programmable Wait States

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to Section 28. “Parallel Mas-
ter Port (PMP)” (DS70576) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (

www.microchip.com

).

2: Some registers and associated bits

described in this section may not be
available on all devices. Refer to

 in

this data sheet for device-specific register
and bit information.

PMA<0>

PMA<14>

PMA<15>

PMBE

PMRD

PMWR

PMD<7:0>

PMENB

PMRD/PMWR

PMCS1

PMA<1>

PMA<13:2>

PMALL

PMALH

PMA<7:0>
PMA<15:8>

PMCS2

Address Bus
Data Bus
Control Lines

8-Bit Data (with or without multiplexed addressing)

Up to 16-Bit Address