Microchip Technology MA330025-1 Data Sheet

DS70616G-page 48

 2009-2012 Microchip Technology Inc.

4.1.1

PROGRAM MEMORY 
ORGANIZATION

The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (

). 

Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.

4.1.2

INTERRUPT AND TRAP VECTORS

All devices reserve the addresses between 0x00000
and 0x000200 for hard-coded program execution vec-
tors. A hardware Reset vector is provided to redirect
code execution from the default value of the PC on
device Reset to the actual start of code. A GOTO
instruction is programmed by the user application at
address 0x000000 of the primary Flash memory or at
address 0x7FFFFC of the auxiliary Flash memory, with
the actual address for the start of code at address
0x000002 of the primary Flash memory or at address
0x7FFFFE of the auxiliary Flash memory. Reset Target
Vector Select bit (RSTPRI) in the FPOR Configuration
register controls whether primary or auxiliary Flash
Reset location is used. 
A more detailed discussion of the interrupt vector
tables is provided in 

0

8

16

PC Address

0x000000
0x000002
0x000004
0x000006

23

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001
0x000003
0x000005
0x000007

msw

Address

(lsw Address)