Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 483
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
29.5
JTAG Interface
dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices implement a
JTAG interface, which supports boundary scan device
testing. Detailed information on this interface is
provided in future revisions of the document.
PIC24EPXXX(GP/GU)810/814 devices implement a
JTAG interface, which supports boundary scan device
testing. Detailed information on this interface is
provided in future revisions of the document.
29.6
In-Circuit Serial Programming
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data, and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33E/PIC24E Flash
Programming Specification” (DS70619) for details
about In-Circuit Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
PIC24EPXXX(GP/GU)810/814 devices can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data, and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33E/PIC24E Flash
Programming Specification” (DS70619) for details
about In-Circuit Serial Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
29.7
In-Circuit Debugger
When MPLAB
®
ICD 3 or REAL ICE™ is selected as a
debugger, the in-circuit debugging functionality is
enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging
functionality is controlled through the PGECx (Emula-
tion/Debug Clock) and PGEDx (Emulation/Debug
Data) pin functions.
enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging
functionality is controlled through the PGECx (Emula-
tion/Debug Clock) and PGEDx (Emulation/Debug
Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
DD
, V
SS
and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
29.8
Code Protection and
CodeGuard™ Security
CodeGuard™ Security
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices offer basic
implementation of CodeGuard Security that supports
only General Segment (GS) security. This feature helps
protect individual Intellectual Property in collaborative
system designs.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33E implemented. The following sections
provide an overview of these features.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices do not support
Boot Segment (BS), Secure Segment (SS) and RAM
protection.
PIC24EPXXX(GP/GU)810/814 devices offer basic
implementation of CodeGuard Security that supports
only General Segment (GS) security. This feature helps
protect individual Intellectual Property in collaborative
system designs.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33E implemented. The following sections
provide an overview of these features.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices do not support
Boot Segment (BS), Secure Segment (SS) and RAM
protection.
Note:
Refer to Section 24. “Programming
and Diagnostics” (DS70608) of the
“dsPIC33E/PIC24E Family Reference
Manual” for further information on usage,
configuration and operation of the JTAG
interface.
and Diagnostics” (DS70608) of the
“dsPIC33E/PIC24E Family Reference
Manual” for further information on usage,
configuration and operation of the JTAG
interface.
Note:
Refer to Section 23. “CodeGuard™
Security” (DS70634) of the “dsPIC33E/
PIC24E Family Reference Manual” for
further information on usage, configuration
and operation of CodeGuard Security.
Security” (DS70634) of the “dsPIC33E/
PIC24E Family Reference Manual” for
further information on usage, configuration
and operation of CodeGuard Security.