Microchip Technology MA330025-1 Data Sheet

DS70616G-page 54

 2009-2012 Microchip Technology Inc.

4.2.5

X AND Y DATA SPACES

The dsPIC33EPXXX(GP/MC/MU)806/810/814 core
has two data spaces, X and Y. These data spaces can
be considered either separate (for some DSP
instructions), or as one unified linear address range (for
MCU instructions). The data spaces are accessed
using two Address Generation Units (AGUs) and
separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The PIC24EPXXX(GP/GU)806/810/814 devices do not
have a Y data space and a Y AGU. For these devices,
the entire data space is treated as X data space.
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class). 
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR,  ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths. 
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed
Addressing mode is only supported for writes to X data
space. Modulo Addressing and Bit-Reversed
Addressing are not present in PIC24EPXXX(GP/
GU)806/810/814 devices.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable. 

4.2.6

DMA RAM

Each dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 device contains
4 Kbytes of dual ported DMA RAM located at the end
of Y data RAM and is part of Y data space. Memory
locations in the DMA RAM space are accessible simul-
taneously by the CPU and the DMA Controller module.
DMA RAM is utilized by the DMA controller to store
data to be transferred to various peripherals using
DMA, as well as data transferred from various periph-
erals using DMA. The DMA RAM can be accessed by
the DMA controller without having to steal cycles from
the CPU.

When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.

Many useful resources related to the Program Memory
are provided on the main product page of the Microchip
web site for the devices listed in this data sheet. This
product page, which can be accessed using this 

contains the latest updates and additional information.

4.3.1

KEY RESOURCES

• Section 4. “Program Memory” (DS70612) in the 

• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33E/PIC24E Family Reference 

Manual” Sections

• Development Tools

 through 

 provide mapping tables

for all Special Function Registers (SFRs).

Note 1: DMA RAM can be used for general

purpose data storage if the DMA function
is not required in an application.

2: On PIC24EPXXX(GP/GU)806/810/814

devices, DMA RAM is located at the end
of X data RAM and is part of X data
space.

In the event you are not able to access the
product page using the link above, enter
this URL in your browser: