Microchip Technology MA330025-1 Data Sheet
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 564
2009-2012 Microchip Technology Inc.
TABLE 32-59: DCI MODULE (MULTI-CHANNEL, I
2
S MODES) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
T
A
+85°C for Industrial
-40°C
T
A
+125°C for Extended
Param. Symbol
Characteristic
Min.
Typ.
(
)
Max.
Units
Conditions
CS10
T
CSCKL
CSCK Input Low Time
(CSCK pin is an input)
(CSCK pin is an input)
T
CY
/2 + 20
—
—
ns
CSCK Output Low Time
(CSCK pin is an output)
30
—
—
ns
CS11
T
CSCKH
CSCK Input High Time
(CSCK pin is an input)
(CSCK pin is an input)
T
CY
/2 + 20
—
—
ns
CSCK Output High Time
(CSCK pin is an output)
30
—
—
ns
CS20
T
CSCKF
CSCK Output Fall Time
(CSCK pin is an output)
(CSCK pin is an output)
—
—
—
ns
CS21
T
CSCKR
CSCK Output Rise Time
(CSCK pin is an output)
(CSCK pin is an output)
—
—
—
ns
CS30
T
CSDOF
CSDO Data Output Fall Time
—
—
—
ns
See Parameter
CS31
T
CSDOR
CSDO Data Output Rise Time
—
—
—
ns
See Parameter
CS35
T
DV
Clock Edge to CSDO Data Valid
—
—
10
ns
CS36
T
DIV
Clock Edge to CSDO Tri-Stated
10
—
20
ns
CS40
T
CSDI
Setup Time of CSDI Data Input
to CSCK Edge (CSCK pin is
input or output)
to CSCK Edge (CSCK pin is
input or output)
20
—
—
ns
CS41
T
HCSDI
Hold Time of CSDI Data Input to
CSCK Edge (CSCK pin is input
or output)
CSCK Edge (CSCK pin is input
or output)
20
—
—
ns
CS50
T
COFSF
COFS Fall Time
(COFS pin is output)
(COFS pin is output)
—
—
—
ns
CS51
T
COFSR
COFS Rise Time
(COFS pin is output)
(COFS pin is output)
—
—
—
ns
CS55
T
SCOFS
Setup Time of COFS Data Input
to CSCK Edge (COFS pin is
input)
to CSCK Edge (COFS pin is
input)
20
—
—
ns
CS56
T
HCOFS
Hold Time of COFS Data Input to
CSCK Edge (COFS pin is input)
CSCK Edge (COFS pin is input)
20
—
—
ns
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.