Microchip Technology MA330024 Data Sheet
2009-2014 Microchip Technology Inc.
DS70000591F-page 119
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 6-2:
SYSTEM RESET TIMING
Reset
Run
Device Status
V
DD
V
POR
V
BOR
POR
BOR
SYSRST
T
PWRT
T
POR
T
BOR
Oscillator Clock
T
OSCD
T
OST
T
LOCK
Time
FSCM
T
FSCM
1
2
3
4
5
6
Note
1:
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until
V
V
DD
crosses the V
POR
threshold and the delay, T
POR
, has elapsed.
2:
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
DD
crosses the V
BOR
threshold and the delay, T
BOR
, has elapsed. The delay, T
BOR
, ensures the voltage regulator output becomes stable.
3:
PWRT Timer: The programmable Power-up Timer (PWRT) continues to hold the processor in Reset for a
specific period of time (T
specific period of time (T
PWRT
) after a BOR. The delay, T
PWRT
, ensures that the system power supplies have
stabilized at the appropriate level for full-speed operation. After the delay, T
PWRT
has elapsed and the SYSRST
becomes inactive, which in turn, enables the selected oscillator to start generating clock cycles.
4:
Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
for more information.
5:
When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
6:
If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is
ready and the delay, T
ready and the delay, T
FSCM
, has elapsed.
TABLE 6-2:
OSCILLATOR DELAY
Symbol
Parameter
Value
V
POR
POR Threshold
1.8V nominal
T
POR
POR Extension Time
30
s maximum
V
BOR
BOR Threshold
2.5V nominal
T
BOR
BOR Extension Time
100
s maximum
T
PWRT
Programmable
Power-up Time Delay
Power-up Time Delay
0-128 ms nominal
T
FSCM
Fail-Safe Clock Monitor
Delay
Delay
900
s maximum
Note:
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
operating parameters within specification.
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all
operating parameters within specification.