Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 164
2009-2014 Microchip Technology Inc.
REGISTER 7-33:
IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
R/W-0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
QEI1IP<2:0>: QEI1 Interrupt Priority bits
111
= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001
•
•
001
= Interrupt is Priority 1
000
= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PSEMIP<2:0>: PWM Special Event Match Interrupt Priority bits
111
= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001
•
•
001
= Interrupt is Priority 1
000
= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’