Microchip Technology TDGL019 Data Sheet
PIC32MX1XX/2XX
DS60001168F-page 288
© 2011-2014 Microchip Technology Inc.
30.1
DC Characteristics
TABLE 30-2:
DC CHARACTERISTICS: OPERATING CURRENT (I
DD
)
TABLE 30-1:
OPERATING MIPS VS. VOLTAGE
Characteristic
V
DD
Range
(in Volts)
(1)
Temp. Range
(in °C)
Max. Frequency
PIC32MX1XX/2XX
MDC5
2.3-3.6V
-40°C to +85°C
50 MHz
Note 1:
Overall functional device operation at V
BORMIN
< V
DD
< V
DDMIN
is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below V
DDMIN
. Refer to
for BOR values.
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
≤ T
A
≤ +85°C for Industrial
Parameter
No.
Typical
(3)
Max.
Units
Conditions
Operating Current (I
DD
) (Note 1, 2)
MDC24
25
37
mA
50 MHz
Note 1:
A device’s I
DD
supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2:
The test conditions for I
DD
measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, Program Flash, and SRAM data memory are operational, SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
• MCLR = V
DD
• CPU executing while(1) statement from Flash
3:
RTCC and JTAG are disabled
4:
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
Parameters are for design guidance only and are not tested.